Integrated circuit electronic memory arrays having a plurality of one device FET memory cells are notoriously well known in the art. Such an array of memory cells was first proposed in Dennard U.S. Pat. No. 3,387,286 entitled: "Field-Effect Transistor Memory". Subsequently, various improvements were made primarily in the fabrication processes in integrated semiconductor circuit technology.
One such semiconductor integrated circuit process is the self-aligned silicon gate process. In this FET process, silicon gate regions (usually polysilicon) are formed prior to the formation of doped source and drain regions. Source and drain regions are known to be formed by both diffusion and ion implantation processes and are self-aligned to the gate region by virtue of the fact that the gate is utilized as the mask. This silicon gate technology, which is a polysilicon process, has been extended to several layers of polysilicon conductors such as double polysilicon (DPS) and triple polysilicon (TPS) etc.
In this technology, it is common practice for the bit line to be an elongated doped N+ region; which same region also forms the drain or source region of the one device FET memory cell. Drain and source regions are interchangeable in FETs and depend on the applied bias voltages. The bit line is electrically integral with (e.g. connected to) the doped region farthest from the capacitor. The distributed capacitance along the length of such a doped bit line is relatively high. Since the signal strength at the sense amplifier input (connected to the bit line) is a function of the transfer ratio (memory cell capacitance/bit line capacitance), a large bit line capacitance tends to reduce the useful input signal to the sense amplifier. To improve the transfer ratio, the size of the storage capacitor in the memory cell can be increased. The added space occupied by such a storage capacitor is undesirable because it reduces the number of memory cells that can be put on a semiconductor chip of a given size. Moreover, the doped bit line also has a finite resistance which together with the various capacitances including the storage capacitor affect the rise time of pulses being transferred in and out of the storage capacitor. Thus, a larger storage capacitor could result in a slower operating memory cell.
It becomes apparent that a conductive bit line formed above the silicon substrate surface from a metal such as aluminum, for example, would have a substantially reduced resistance in comparison with a doped bit line. More importantly, the dielectric insulation between such an aluminum bit line and other conductive lines and circuit elements results in a substantially reduced bit line capacitance with a corresponding substantial improvement in the transfer ratio.
For this reason, the prior art has addressed the concept of memory arrays utilizing metal bit lines. For example, see Kiyoo Itoh et al., "A High-Speed 16 K Bit NMOS Random Access Memory", IEEE J. Solid-State Circuits SC-11, pp. 585-590, October 1976. Although this article describes a device with the advantages of metal bit lines, it is accompanied by a number of disadvantages in semiconductor integrated circuit fabrication. For example, it results in bit lines that are excessively long for the number of bits along such a bit line. In addition to being wasteful of space, there occurs an excessive capacitance between the bit line and the polysilicon from which it is insulated by a dielectric such as silicon dioxide. A very significant disadvantage of such a prior art metal bit line configuration is that the bit line pitch (width of one bit line) is too small to properly fit a sense amplifier at the end of the bit line. Thus, the spacing between bit lines must be increased in order to properly accommodate sense amplifiers, further decreasing the packing density of the array.